1. Field of the Invention
The present invention relates to multiple processors in computer systems, and more particularly to bus arbitration between multiple processors in computer systems with single processor arbitration schemes.
2. Description of the Prior Art
The personal computer industry is a vibrant and growing field that continues to evolve as new innovations occur. The driving force behind this innovation has been the increasing demand for faster and more powerful personal computers. In order to meet this demand, computer designers have used various methods to increase the speed with which personal computers can process instructions.
Historically the personal computer has developed as a system incorporating a single microprocessor to handle all instruction execution. The microprocessor is the key working unit or "brains" of the personal computer, and its task is to handle all of the instructions that programs give it in the form of computer software. One method that is being used to increase the speed of the personal computer system is the incorporation of multiple microprocessors operating in parallel into a computer system. With the use of multiple processors, or multiprocessing, each microprocessor can be working on a different task at the same time. Systems that incorporate multiprocessing generally use standard microprocessors that operate off of a common bus and share a common memory. Due to the large amount of existing single processor-based computer systems, it would be desirable to be able to incorporate multiple processors into these single processor systems with minimal changes to the system.
One of the most important considerations in the design of a computer system involves the communication of data and synchronization/control signals between all of the various components which comprise it. In personal computer systems compatible with those previously manufactured and sold by International Business Machines Corp. (IBM), communication between the various components which comprise the computer is accomplished via a "shared bus" architecture, wherein the functional units of the system are connected by a common collection of conductive lines called a bus. In such an organization, only one module at a time can exert control over the use of the shared bus, and contention among the units which require the use of the bus must be resolved in some manner. This problem of resolving bus contention between the various units which require the bus is generally known as arbitration. The problem of bus arbitration is even more pronounced in a multiprocessing environment due to the effect of additional microprocessors vying for control of the bus.
Personal computers that have been developed to incorporate a single microprocessor have generally included an arbitration scheme that assumes only a single processor will be present within the system. Therefore, if an incorporation of multiple microprocessors into a single processor-based computer system is desired, it is necessary that the fact that multiple processors exist within the system be invisible to the system's arbitration scheme.
Background on the single processor-based arbitration scheme in which the present invention is incorporated is deemed appropriate. In 1981 IBM introduced the personal computer, the IBM PC, which was based on the Intel Corporation (Intel) 8088 microprocessor. The bus architecture used in the original IBM PC and the PC/AT has generally become known as the Industry Standard Architecture (ISA). Computer systems developed according to the ISA had a priority scheme wherein the processor had control of the bus, except when the direct memory access controller requested and received control or when a memory refresh cycle was occurring.
Many improvements and extensions have been made on the ISA, the latest development being an extended version of the ISA referred to as the Extended Industry Standard Architecture (EISA) that includes a 32-bit data bus, a 32-bit address bus and full backwards compatibility with ISA devices and software. In conjunction with the development of EISA, Intel Corporation, a major manufacturer of computer components and devices for IBM-compatible personal computers, developed a device referred to as the Integrated System Peripheral (ISP) that is designed to be used in an EISA system. The ISP integrates many of the EISA required functions into a single device, including a 7 channel, 32-bit DMA controller, an interrupt controller module, a timer/counter module, a refresh address generator, and a system arbiter, among others. The arbitration scheme that the ISP includes is intended for a single processor-based system and includes several levels of priority with each level incorporating a rotating priority scheme. The system arbiter in the ISP generally conducts arbitration for control of the bus between four devices, these being the direct memory access (DMA) system, the memory refresh system, the various bus masters, and a single CPU.